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<title>VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values </title></head>
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<h1>VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F38.W1 98 /r</p>
<p>VFMADD132PD xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, add to xmm2 and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F38.W1 A8 /r</p>
<p>VFMADD213PD xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/mem and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F38.W1 B8 /r</p>
<p>VFMADD231PD xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.W1 98 /r</p>
<p>VFMADD132PD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, add to ymm2 and put result in ymm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.W1 A8 /r</p>
<p>VFMADD213PD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/mem and put result in ymm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.W1 B8 /r</p>
<p>VFMADD231PD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>FMA</td>
<td>Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, add to ymm1 and put result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W1 98 /r</p>
<p>VFMADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>RVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, add to xmm2 and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W1 A8 /r</p>
<p>VFMADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/m128/m64bcst and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W1 B8 /r</p>
<p>VFMADD231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, add to xmm1 and put result in xmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W1 98 /r</p>
<p>VFMADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, add to ymm2 and put result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W1 A8 /r</p>
<p>VFMADD213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/m256/m64bcst and put result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W1 B8 /r</p>
<p>VFMADD231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, add to ymm1 and put result in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W1 98 /r</p>
<p>VFMADD132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, add to zmm2 and put result in zmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W1 A8 /r</p>
<p>VFMADD213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed double-precision floating-point values from zmm1 and zmm2, add to zmm3/m512/m64bcst and put result in zmm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W1 B8 /r</p>
<p>VFMADD231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, add to zmm1 and put result in zmm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (r, w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (r, w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs a set of SIMD multiply-add computation on packed double-precision floating-point values using three source operands and writes the multiply-add results in the destination operand. The destination operand is also the first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD register or a memory location.</p>
<p>VFMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).</p>
<p>VFMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).</p>
<p>VFMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).</p>
<p>EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.</p>
<p>VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.</p>
<p>VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.</p>
<p><strong>Operation</strong></p>
<p>In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).</p>
<p><strong>VFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM-1 {</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+63:n] (cid:197) RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM-1 {</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+63:n] (cid:197) RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)</strong></p>
<p>IF (VEX.128) THEN</p>
<p>MAXNUM (cid:197)2</p>
<p>ELSEIF (VEX.256)</p>
<p>MAXNUM (cid:197) 4</p>
<p>FI</p>
<p>For i = 0 to MAXNUM-1 {</p>
<p>n (cid:197) 64*i;</p>
<p>DEST[n+63:n] (cid:197) RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])</p>
<p>}</p>
<p>IF (VEX.128) THEN</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p>ELSEIF (VEX.256)</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p>FI</p>
<p><strong>VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF (VL = 512) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1)</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])</p>
<p>ELSE</p>
<p>DEST[i+63:i] (cid:197)</p>
<p>RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VFMADDxxxPD __m512d _mm512_fmadd_pd(__m512d a, __m512d b, __m512d c);</p>
<p>VFMADDxxxPD __m512d _mm512_fmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);</p>
<p>VFMADDxxxPD __m512d _mm512_mask_fmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);</p>
<p>VFMADDxxxPD __m512d _mm512_maskz_fmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);</p>
<p>VFMADDxxxPD __m512d _mm512_mask3_fmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);</p>
<p>VFMADDxxxPD __m512d _mm512_mask_fmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);</p>
<p>VFMADDxxxPD __m512d _mm512_maskz_fmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);</p>
<p>VFMADDxxxPD __m512d _mm512_mask3_fmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);</p>
<p>VFMADDxxxPD __m256d _mm256_mask_fmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);</p>
<p>VFMADDxxxPD __m256d _mm256_maskz_fmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);</p>
<p>VFMADDxxxPD __m256d _mm256_mask3_fmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);</p>
<p>VFMADDxxxPD __m128d _mm_mask_fmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);</p>
<p>VFMADDxxxPD __m128d _mm_maskz_fmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);</p>
<p>VFMADDxxxPD __m128d _mm_mask3_fmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);</p>
<p>VFMADDxxxPD __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);</p>
<p>VFMADDxxxPD __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Overflow, Underflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>VEX-encoded instructions, see Exceptions Type 2.</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E2.</td></tr></table></body></html>